1. Field of the Invention
The present invention generally concerns pipelined analog to digital (A/D) conversion in which is performed noisy digital to analog (D/A) conversion, and pipelined analog to digital (A/D) converters internally incorporating noisy digital to analog (D/A) converters.
The present invention particularly concerns noise, and more particularly noise due to component mismatch, occurring in A/D conversion and in A/D convertersxe2x80x94particularly as are used in D/A conversion and convertersxe2x80x94and the abatement and/or cancellation of this noise.
2. Description of the Prior Art
2.1 General Background
It is known that digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) have systemic sources of noise, and that these noise sources can sometimes be abated, or canceled.
For example, U.S. Pat. No. 5,684,482 for SPECTRAL SHAPING OF CIRCUIT ERRORS IN DIGITAL-TO-ANALOG CONVERTERS to the selfsame inventor Galton as is the present invention concerns a general digital-to-analog (DAC) topology that spectrally shapes the DAC conversion noise caused by analog circuit mismatches. In particular, certain highly practical first-order and second-order noise-shaping DACs that are special cases of a general topology are taught. The topology extends the practicality of using noise-shaping DACs in xcex94xcexa3 data converters. A first-order DAC shown in the patent is at least as hardware efficient as previously known DACs, but offers the advantage that it is amenable to a simple dithering technique capable of eliminating spurious tones. A second-order DAC shown in the patent is more hardware efficient than previously known DACs, and generally has a large spurious-free dynamic range without any dithering. DACs with other types of noise-shaping characteristics (e.g., bandpass noise-shaping characteristics) may be designed based on general DAC topology.
2.2 Specific Background
Unlike other types of noise in a conventional pipelined analog to digital converter (ADC), noise introduced by a first-stage digital to analog converter (DAC) that is within the ADC is not attenuated or canceled along the pipeline, so it tends to be the dominant contributor of overall ADC error. See S. H. Lewis and P. R. Gray, xe2x80x9cA pipelined 5-Msample/s 9-bit analog-to-digital converter,xe2x80x9d IEEE Journal of Solid State Circuits, vol. SC-22, no. 6, pp. 954-961, Dec. 1987. See also S. Sutarja and P. R. Gray, xe2x80x9cA pipelined 13-bit 250-ks/s 5-V analog-to-digital converter,xe2x80x9d IEEE Journal of Solid State Circuits, vol. 23, no. 6, pp. 1316-1323, Dec. 1988.
In typical switched-capacitor implementations, most of this DAC noise arises from static capacitor mismatches. With present VLSI circuit technology it is difficult to match capacitors to better than 0.1%. This translates into an A/D conversion limit of about 11 bits in pipelined ADC architectures not having some form of error cancellation.
Pipelined analog-to-digital converters (ADCs) tend to be sensitive to component mismatches in their internal digital-to-analog converters (DACs). These component mismatches give rise to error, referred to as DAC noise, which is not attenuated or canceled along the ADC pipeline as are other types of noise. The present invention contemplates an all-digital technique that significantly mitigates this problem.
In particular, the present invention concerns a technique for digital cancellation of DAC noise arising from static analog errors such as capacitor mismatches. The technique is referred to as DAC noise cancellation (DNC). It differs from most other cancellation schemes in that it measures and cancels the DAC noise continuously during normal operation of the ADC; no special calibration signal nor auto calibration phase is required prior to A/D conversion.
In the presence of realistic component matching limitations, the technique of the present invention improves the overall ADC accuracy by several bits with only moderate digital hardware complexity. Both the measurement and cancellation of DAC noise are entirely performed using digital logic, so no additional analog circuits are required over those of a conventional pipelined ADC. The digital complexity of the DNC processing is well within practical limits for typical CMOS and BiCMOS circuit technologies.
1. Error Correctionxe2x80x94Particularly Digital Cancellation of D/A Converter Noisexe2x80x94in Pipelined A/D Converters
In one of its aspects the present invention in embodied in an improvement to a multistage pipelined Analog-to-Digital Converter (ADC). The improvement is directed to error correction, and more particularly to digital cancellation of noisexe2x80x94most particularly as results from mismatch between componentsxe2x80x94principally arising in Digital-to-Analog Converters (DACs) that are within each stage of the multistage ADC.
The improvement is thus to a conventional multistage pipelined Analog-to-Digital Converter (ADC)xe2x80x94receiving an analog input signalxe2x80x94that has a plurality of stages each connected one to the next by an interstage amplifier. Each stage has a flash digital-to-analog converter (DAC)xe2x80x94a DAC of the first stage receiving the analog input signal while DACs of subsequent stages receive analog signals each from a respective interstage amplifierxe2x80x94producing a multi-level digital signal. A digital-to-analog converter (DAC) in each stage converts an associated produced multi-level digital signal to an associated intermediate analog signal. Each intermediate analog signal is feed both to (i) a subtractor of the intermediate analog signal from the associated analog signal received by the stage to produce an analog difference signal that is fed to the interstage amplifier of a next following stage, and also to (ii) a thermometer encoder producing an associated digital output signal. The digital output signals of all the plurality of stages are summed to produce an overall ADC digital output signal. This construction, and this co-action between components, is conventional.
The present invention constitutes an improvement where a flash digital-to-analog converter (DAC) (which is of a dynamic element matching (DEM) type) within each stage is enhanced so as to produce, as well as an associated intermediate analog signal, a (i) plurality of random bits and a (ii) plurality of parity bits. To this enhanced DAC is added within each stage a new (i) Digital Noise Cancellation (DNC) logic circuit, and (ii) a subtractor.
The DNC logic circuit of each stage receives (1) the (i) plurality of random bits and the (ii) plurality of parity bits from the associated DEM-type DAC and (2) a digitized residue sum of the digital output signals of all stages beyond a stage of which the DNC logic circuit is a part, in order to produce an error estimate for the stage.
The subtractor of each stage subtracts the error estimate received from the DNC logic circuit of the stage from, in succession stage by stage, the ADC digital output signal so as to produce, ultimately, a ADC digital output signal that is corrected for noise arising in, inter alia, the DAC of each stage.
The Digital Noise Cancellation (DNC) logic circuit for each stage preferably includes (1) an adder of the plurality of random bits and the digitized residue to produce an intermediary result; (2) a three-level requantizer of the intermediary result producing a three-level signal; (3) a plurality of channels, receiving the three-level signal, and (4) an adder summing outputs of all the channels to produce the error estimate for the stage.
Each (3) channel preferably includes (3a) a first multiplier multiplying the three-level signal and an associated one of the random bits, (3b) a second multiplier multiplying an output from the first multiplier and an associated one of the random bits, (3c) an averager of a predetermined number of outputs from the second multiplier producing a true average, (3d) a third multiplier multiplying the true average and the associated one of the random bits, and (3e) a fourth multiplier multiplying an output from the third multiplier and the associated one of the random bits. The (4) adder thus sums the outputs of the fourth multipliers of all the channels to produce the error estimate for the stage.
The DEM-type DAC preferably includes a digital encoder dividing an N-level digital input signal into multiple digital output signals. Each such digital encoder preferably includes (1) two or more switching blocks each having a digital input signal and two digital output signals where a sum of the two digital output signals equals the digital input signal; and (2) a converter converting a sum of the multiple digital output signals as arise from all the digital encoder into a nominally equivalent analog signal.
2. Improvement to a Multi-stage Pipelined A/D Converter
The embodiment of the present invention as an improvement to a multistage pipelined Analog-to-Digital Converter may be still more succinctly expressed if the entire ADC, and the improvement thereto, are reduced to their core essence.
In a multistage analog-to-digital converter (ADC) having in each stage (i) a flash digital-to-analog converter (DAC) producing a digital signal, and (ii) a thermometer encoder producing from the DAC digital signal another digital signal summable with the like signals of the encoders of other stages to produce, ultimately, an ADC digital output signal, the improvement of the present invention reduces, in essence, to just three elements:
First, an enhancement to the flash DAC of each stage serves to cause the DAC to produce, as well as the DAC digital signal, both random bits and parity bits.
Second, a Digital Noise Cancellation (DNC) logic circuit at each stage receives (1) these random bits and parity bits from the stage""s enhanced DAC, and also (2) the digital signal from the stages""s thermometer encoder, to produce a stage error signal.
Finally, a subtractor receives the stage error signal from the DNC logic circuit of the stage so as to error correct the ADC digital output signal and transmit it to a next stage. A succession of subtractors in all stages operate on the ADC digital output signal so as to make that, ultimately, this signal becomes corrected for, inter alia, signal error (i.e., noise) rising from, inter alia, component mismatch in the flash DACs.
3. A Method of Correcting in a Digital Output Signal of a Multistage Analog-to-Digital Converter (ADC) Error (Noise) Resultant From, Inter Alia, Component Mismatch in Flash Digital-to-Analog Converters (DACs) That are Within Each Stage of the Multistage ADC
In yet another of its aspects the present invention is embodied in a method of correcting in a digital output signal of a multistage analog-to-digital converter (ADC) error (i.e., noise) resultant from, inter alia, component mismatch in flash digital-to-analog converters (DACs) that are within each stage of the multistage ADC.
The signal error correction method includes (1) producing in an enhanced flash DAC of each stage both (i) random bits and (ii) parity bits as well as a (iii) DAC digital signal; (2) producing in a Digital Noise Cancellation (DNC) logic circuit of each stage from the (i) random bits and (ii) parity bits of the stage""s enhanced DAC, plus (iv) a digital signal from a thermometer encoder of the stage that has previously encoded an ADC digital signal of the stage, a stage error signal; and (3) subtracting in a subtractor of each stage the stage""s error signal produced in the DNC logic circuit from an ADC digital output signal of the entire ADC, passing onward to a next successive stage the corrected ADC digital output signal until, at the conclusion of all stages the ADC digital output signal is corrected for, inter alia, error in this signal rising from component mismatch in the flash DACs.
These and other aspects and attributes of the present invention will become increasingly clear upon reference to the following drawings and accompanying specification.